RESP_ERR_STAT_EN=Val_0x0, DATA_CRC_ERR_STAT_EN=Val_0x0, AUTO_CMD_ERR_STAT_EN=Val_0x0, CMD_IDX_ERR_STAT_EN=Val_0x0, CMD_END_BIT_ERR_STAT_EN=Val_0x0, ADMA_ERR_STAT_EN=Val_0x0, CMD_CRC_ERR_STAT_EN=Val_0x0, CMD_TOUT_ERR_STAT_EN=Val_0x0, CUR_LMT_ERR_STAT_EN=Val_0x0, DATA_TOUT_ERR_STAT_EN=Val_0x0, DATA_END_BIT_ERR_STAT_EN=Val_0x0, BOOT_ACK_ERR_STAT_EN=Val_0x0
Error Interrupt Status Enable Register
| CMD_TOUT_ERR_STAT_EN | Command Timeout Error Status Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CMD_CRC_ERR_STAT_EN | Command CRC Error Status Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CMD_END_BIT_ERR_STAT_EN | Command End Bit Error Status Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CMD_IDX_ERR_STAT_EN | Command Index Error Status Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| DATA_TOUT_ERR_STAT_EN | Data Timeout Error Status Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| DATA_CRC_ERR_STAT_EN | Data CRC Error Status Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| DATA_END_BIT_ERR_STAT_EN | Data End Bit Error Status Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CUR_LMT_ERR_STAT_EN | Current Limit Error Status Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| AUTO_CMD_ERR_STAT_EN | Auto CMD Error Status Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| ADMA_ERR_STAT_EN | ADMA Error Status Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| RESP_ERR_STAT_EN | Response Error Status Enable (SD mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| BOOT_ACK_ERR_STAT_EN | Boot Acknowledgment Error (eMMC mode only). Setting this bit to 0x1 enables setting of Boot Acknowledgment Error in the SDMMC_ERROR_INT_STAT_R register. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |